Static Random Access Memories (SRAMs) contain millions of extremely thin vias, long metal rails, and a large number of transistors in multiple layers of metal. Owing to the large number of elements, the probability of failure of a device is not negligible. One of the most common reasons for SRAM failures is a single defect in the memory core region, e.g. contact/via malformation or a malformed transistor. Incorporating redundancy schemes can compensate this type of failure in SRAMs. The redundancy schemes ensure normal functioning of the memory device by compensating for most single defects, thereby improving yield and reducing the effective cost of the device.
Current row and column redundancy schemes cover single defects efficiently only for unshared components. However, in practice, many contacts and vias that are potential defects are shared by adjacent cells to reduce device area. Whether the fault can be corrected in such resource-shared devices using the conventional redundancy schemes depends upon the location of the defect, and hence, the percentage fault coverage due to the single defect is not independent of memory architecture and therefore, is generally unsatisfactory. There is a need for improving the efficacy of redundancy schemes.
There are two basic types of the redundancy schemes, row redundancy and column redundancy. Row redundancy schemes are not popular owing to the fact that the fault coverage provided by them is relatively less due to the high sharing of resources. On the other hand, row redundancy schemes provide the advantages of reduced settling time, simpler circuitry, and higher area efficiency. Further, the testability of redundant rows in the row redundancy scheme is simpler and faster due the fact that the memory cells are designed for efficient row-by-row access.
U.S. Pat. No. 6,314,030 discloses a segmented row repair scheme. In this patent, the memory cell array is divided into segments of rows with each segment containing a redundant row. The repair scheme disclosed suffers from a number of constraints owing to the fact that each segment contains one redundant row that requires an address storage block, thereby increasing the size and cost of the device. The arrangement also makes it difficult to test the redundant rows. The scheme also does not provide any solution for the failure of shared elements.
FIG. 1 illustrates a column redundancy scheme for semiconductor memory architecture 100 according to U.S. Pat. No. 5,742,556. In this scheme the write multiplexers 102 are located prior to the write bit line drivers 104. The fuse data corresponding to the defective column is decoded in the columns by the combination of AND gates 112 and OR gates 114 for each regular column. The AND 112 and OR 114 gates form a decision unit that determines whether an actual bitline is to be used or an adjacent bitline is to be used. Since the inputs to AND gates 112 are connected in a sequential count arrangement, only one AND gate 112 is activated for any combination of programmed fuses. The active AND gate 112 corresponds to the defective regular column. The active AND gate output activates the associated OR gate 114 and the signal then ripples sequentially through the OR gates 114 to the “right”. Hence, from the defective column to the right, the SRAM columns are all shifted to the right and, finally at the far right, the redundant column which includes its own write driver 104 is also used.
In this type of redundancy scheme, the built in self-test (BIST) within the memory devices introduces a significant delay during soft repair runs because of the rippling of signals causing higher settling times. The arrangement also requires complex circuitry to enable the rippling of data and requires large area for its implementation. Further, such a column redundancy scheme does not provide immunity to the memory device against failure of a shared component. Furthermore, the probability of the failure of two rows/columns in the event of single component malformation is a linear function of the number shared components in the peripheral circuitry. A single row or single column redundancy scheme can correct only single column or row failures.
Referring to FIG. 2, most of the shared components are located on top and bottom boundaries. These shared component are either shared on the boundary of row R[n−1] and row R[n] or row R[n] and row R[n+1]. In such rectangular memory cell arrangements, the fault coverage in row redundancy schemes are as low as 33%, whereas reduced number of shared component between columns results in percentage fault coverage in columns as much as 75%. On the other hand, in the case of non-rectangular cell (vertical) arrangements, despite of the complicated circuit and higher area penalties column redundancy provides lower coverage than row redundancy. However, it is not possible to achieve 100% percent fault coverage due to a single defect in a memory array or row decoder.